Again, rather than write an essay, I'll just post the last few additions to the changelog for now.
ZX Prism version 0.16 10/10/2014 (non-released, flashed to board)
- Added an extra bit to the Flash ROM address bus so the whole chip can be utilised.
- Added check for CPU_RD on data bus multiplex (fixed Shadow Warriors and several others)
- Added switch to limit memory to 128K (when used, fixes turbo outrun amongst others): OUT 36411,24 limits the page at 0xC000 to pages 0 to 7. OUT 36411,16 re-enables 512K.
- Hooked MMC signals into the glue logic (but the associated IO registers not implemented yet)
- More interrupt tuning for different CPU speeds. Speeds 0-6 (3.5MHz - 28Mhz) work with all games/demos tested. Speed 7 (56MHz) needs further tuning
ZX Prism version 0.15 19/9/2014 (non-released, flashed to board)
- Fixed the main ZX Prism palette. (until this fix, all 3 colour elements were getting set at the same time, meaning you could only select from black and 15 shades of grey!)
- Added write masks for writes to 0x4000 - 0x5FFF (0=currently paged, 1-15=combos of planes). This makes working with the new video modes easier - for example, you can write to multiple planes of a planar mode at the same time, or quickly modify existing software to work in an overlay mode by adding an OUT to the beginning and end of the sprite routine so sprites are written to the shadow screen and overlaid over the main screen to avoid colour clash... etc etc. Care must be taken when using this feature from BASIC (so as not to stop writes to system variables...)
- Removed "64 ink, 4 paper" mode and replaced it with 3 plane planar mode (as defined by Andrew Owen) This mode avoids using memory at 0x6000
- Added overlay options register which selects the attribute decode methods for upper and lower overlays
- Added readable register IN 0x8E3B (36411) returns CPU speed and available system memory:
D4-D7 = Available memory
0000 – 48K
0001 – 128K
0010 – 256K
0011 – 512K
0100 – 1024K
0101 – 2048K
0110 – 4096K
0111 – 8192K
D0-D3 = CPU speed
- Added readable register IN 0x9E3B (40507) returns microcode version (mainly to save me wondering which build of the FPGA code is currently running whilst I'm testing different versions!)
ZX Prism version 0.14 10/9/2014 (non-released, flashed to board)
- In Quartus: Turned on "Auto RAM to Logic Cell Conversion" in Analysis&Synthesis More Settings
- In Quartus: Changed optimization technique to "speed" (from "Balanced") in Analysis&Synthesis More Settings
- In Quartus: Changed Optimization technique to "speed" (from "Balanced") in the Analysis & Synthesis page (diff to above)
- Added attribute decode method 0111 - 64 inks (colours 0-63), 4 papers (colours 0-4) PpIiiiii (this mode was removed in version 0.15)
- -Swapped default colours 0-15 with colours 24-31 so difference between bright 0 and bright 1 is more spectrum-like
- Added a rudimentary floating bus (127 if reading screen, 255 if drawing border) - enough for Arkanoid to run (though the bat and ball flicker!)
- Added overlay mode 1 (Polo Mode) - ink and paper colour 0 and 8 on top layer are treated as transparent and reveal the lower layer.
- Added overlay mode 2 - ink and paper colour 0 on top layer are treated as transparent and reveal the lower layer
- Added 256 colour mode 2 screen 0/1=ink1 colour + pixel data, screen 2/3=ink2 colour+pixel data, paper=border
- Switched to spectrum 128/+2 partial decoding of IO 7FFD to see if that helps with some of the compatibility issues. This will need to change back if port 1FFD etc are used in future.
- Added check for interrupt on function keys (to avoid crashes when changing CPU speeds)
- Started adding an OSD
ZX Prism version 0.13 31/8/2014 (non-released, flashed to board)
- Refactored cpu speed code. Default speed (speed 0000) is now 3.5MHz
- As SRAM and FLASH share FPGA pins, wrote pin multiplexor to facilitate use of both. SRAM signals are mapped to the pins when SRAM_nCS is 0, FLASH signals are mapped when FLASH_nCE is 0. When bothare '1' the pins are set to high impedence so they can be used for other things (eg ROM cartridge, SID, general sound etc - will require fast bus transceiver to translate voltage levels and leave bus at high impedence when FLASH/SRAM are in use)
- For the time being, the memory multiplex is "locked" to talk to SRAM only
- Changed memory mapping so that VRAM is used by both video and cpu for page 5 and 7 (previously CPU writes were being mirrored by VRAM, with CPU reads using SRAM and video reads using VRAM..) this frees up 32K of SRAM for other uses.
- More interrupt tuning (frame length, int start, int duration for speed 0) to fix Mikie (was freezing) and others which weren't detecting keypresses. FUSETEST now detects this as a 48K spectrum due to frame length